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Used an edge detector to generate clock signal

Used a latch to remember signal's past state

Finished a level under 5 minutes thanks to practicing

Took over half an hour to finish a level

Spent an hour by completing a level

Wasted over two hours, but eventually finished the level

Soldered 30 logic components, most of them badly

Soldered 100 logic components

Soldered 250 logic components

Completed all levels on Digital Logic

Completed a level using logic components only

Used a microprocessor due to a shortage of storage capacity

Used 30 words of executable words

Used 100 words of executable code

Used 250 words of executable code

Completed a test sequence in the Sandbox mode

Simulated through 30 test steps

Simulated through 70 test steps

Simulated throught 120 test steps

Have 50 successful step simulations

Have 100 successful step simulations

Have 3:1 ratio of successful tests

Have 1:3 ratio of successful tests

Perform more successful than unsuccessful step simulations